As opposed to planar complementary metal-oxide-semiconductor (CMOS) devices, vertical transport field effect transistor (VTFET) devices are oriented with a vertical fin channel disposed on bottom source and drains and top source and drains disposed on the fin channel. VFETs have been pursued as a potential device option for scaling CMOS to the 5 nanometer (nm) node and beyond.
With a VTFET process flow, the bottom source and drains are often formed by recessing the substrate and then forming doped bottom source and drains at the base of the recessed fins. The bottom extensions are then formed using a drive-in of the dopants into the fins. However, getting a controlled abrupt junction profile by this process is challenging.
Specifically, a higher thermal budget (e.g., from about 900° C. to about 1050° C.) is needed for dopant drive-in to form the extensions in this manner. Diffusion with a high thermal budget ends up with a broad dopant profile which is undesirable.
Therefore, improved techniques for forming bottom extensions with an abrupt dopant profile using a lower thermal budget would be desirable.